Product Overview

USRP-LW N310 is a network software-defined radio (SDR), which provides the deployment of large-scale reliable and fault-tolerant distributed wireless systems. The USRP-LW N310 simplifies the control and management of the SDR system by introducing the ability to perform tasks remotely, such as updating software, restarting, factory reset, self-checking, host/ARM debugging and monitoring system operation. USRP-LW N310 is currently one of the products with the most dense channels in the SDR market, providing 4 channels with 4 receiving channels within a height of 0.5U. The radio frequency front end adopts two ad9371 transceivers, this is a kind of latest analog equipment radio frequency technology. Each channel provides instantaneous bandwidth up to 100 MHz, and covers an extended frequency range from 10 MHz to 6 GHz.

Main Features

· Reliable and fault-tolerant deployment. · Remote management capabilities. · Support independent (embedded) or host-based (network) operation. · 10MHz-6GHz frequency coverage. · Up to 100M instantaneous bandwidth per channel. · Support 4 send and 4 receive at the same time. · Transceiver filter bank. · 16 bit ADC, 14 bit DAC. · Configurable sampling rate: 122.88, 125, and 153.6 MS/s. · Built-in Xilinx Zynq-7100 SoC FPGA. · Dual-core ARM Cortex-A9 CPU 800 MHz. · Dual SPF+ ports (1 Gigabit Ethernet, 10 Gigabit Ethernet, Aurora). · Support external Clock reference and PPS time reference. · Support external RX, TX LO port input. · Built-in GPSDO. · 1 Type A USB host port. · 1 micro-USB port (serial console, JTAG). · Built-in customized linux. · UHD3.11.0 or newer version support. · RFNoC FPGA development framework. · Xilinx Vivado 2017.4 Design Suite (license not included). · Support GNU Radio.

Baseband processor: The USRP-LW N310 baseband processor uses Xilinx's zynq-7100 SOC, which provides a wealth of programmable FPGA for real-time requirements and low-latency processing, and dual-core ARM CPU stand-alone operation. Users can deploy applications on the pre-installed Linux embedded operating system, or use high-speed interfaces such as Gigabit Ethernet host, 10 Gigabit Ethernet. Synchronize: USRP-LW N310 has a flexible reference clock design architecture that supports external PPS, clock reference time reference, external LO input, and gpsdo, which is helpful for the realization of high-channel-count MIMO systems.

Please do not hesitate to contact me if you need any further information.