Description

IS42S16400J-7TLI-TR: DRAMs Parts and Modules - Tape and Reel 

Package: TSOP(II)-54

Mfr. Part#: IS42S16400J-7TLI-TR

Mfr.: ISSI

Datasheet: (e-mail or chat us for PDF file)

ROHS Status: 

Quality: 100% Original

Warranty: 180 days
 

The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 64Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option.

Key Features

• Clock frequency: 200, 166, 143, 133 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
  • 1, 2, 4, 8, full page
• Programmable burst sequence: Sequential/Interleave
• Self refresh modes
• Auto refresh (CBR)
• 4096 refresh cycles every 64 ms (Com, Ind, A1 grade) or 16ms (A2 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Package:
  • 54-pin TSOP II
  • 54-ball TF-BGA (8mm x 8mm)
  • 60-ball TF-BGA (10.1mm x 6.4mm)
• Operating Temperature Range
  • Commercial (0°C to +70°C)
  • Industrial (-40°C to +85°C)
  • Automotive Grade A1 (-40°C to +85°C)
  • Automotive Grade A2 (-40°C to +105°C)

Company Product Line

 

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• Located in Shenzhen, the electronic market center of China.
• 100% guarantee components quality: Genuine Original.
• Sufficient stock on your urgent demand.
• Sophisticated colleagues help you solve problems to reduce your risk with on-demand manufacturing
• Faster shipment: In stock components can ship the same day .
• 24 Hours service 

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